In recent years, the downscaling of interconnect spacing has progressed as higher integration of integrated circuit devices has progressed. In particular, many interconnects are arranged parallel to each other in memory devices such as MRAM (Magneto resistive Random Access Memory) and the like because the interconnects are drawn out from multiple memory cells arranged in a matrix configuration. It is possible to utilize a sidewall process to reduce the arrangement period of the interconnects thus arranged parallel to each other. The sidewall process is a method in which core members are formed in line configurations, slimming of the core members is performed, sidewalls are formed on two sides of the core members, and the core members are subsequently removed. Thereby, multiple sidewalls having an arrangement period of half of the arrangement period of the core members can be formed; and it is possible to form fine interconnects by using the sidewalls as a mask.
However, it is also necessary to downscale the diameters of the contact vias connected to the interconnects as the interconnects are downscaled using the sidewall process.
Thereby, the formation of the contact vias becomes difficult; the contact vias become finer; and the resistance undesirably increases.